A. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor apparatus.
B. Description of the Related Art
An insulated gate bipolar transistor (hereinafter referred to as an “IGBT”), that is one of the power semiconductor devices, exhibits high-speed switching performances and voltage-driven characteristics, which the metal-oxide-semiconductor field-effect transistor (hereinafter referred to as a “MOSFET”) exhibits, and low ON-state voltage characteristics, which the bipolar transistor exhibits. The IGBT's expand the application fields thereof from general-purpose inverters, AC servos, uninterruptible power sources (UPS's), and switching power supplies to boost DC-DC converters for hybrid vehicles.
For manufacturing the semiconductor devices described above, a method described below is proposed in Japanese Unexamined Patent Application Publication No. 2007-036211. A surface structure is formed on the first major surface side of a silicon (Si) substrate. After polishing the second major surface for thinning the Si substrate, a buffer layer and a collector layer are formed on the second major surface side. Then, an aluminum silicon film (AlSi film) is formed on the collector layer. The AlSi film is 0.3 μm or more and 1.0 μm or less in thickness. The Si concentration in the AlSi film is 0.5 wt % or higher and 2 wt % or lower. Preferably, the Si concentration in the AlSi film is 1 wt % or less.
Subsequently to forming the AlSi film, a titanium film (Ti film), a nickel film (Ni film), a gold film (Au film) and such metal films are formed by vacuum deposition or by sputtering to form a collector electrode. The Ti film is a buffer metal film, the Ni film a solder bonding metal film, and Au film a protector metal film, respectively.
In mounting the semiconductor device having electrodes on the front and back surfaces, the collector electrode and such a back surface electrode are bonded to a metal plate working as a heat sink with a solder. The emitter electrode and such a front surface electrode are bonded mainly by the wire bonding technique using an aluminum wire. In these days however, the front surface electrodes are bonded by solder bonding sometimes. By employing the solder bonding technique for bonding the front surface electrodes, the mounting density, the current density, the wiring capacitance reduction for realizing a higher switching speed, and the cooling efficiency of the semiconductor apparatus are improved greatly.
The semiconductor apparatus proposed in Japanese Unexamined Patent Application Publication No. 2002-110893 and described below mounts a semiconductor device thereon by solder bonding. A metal plate functioning as a heat sink is bonded with a solder to the surface of each semiconductor chip, in which a semiconductor device is formed, a second conductor is bonded with a solder to the back surface of the semiconductor chip, and a third conductor is bonded with a solder to the front surface of the heat sink. A step is formed on the heat sink to form a thin portion such that the bonding area between the heat sink and the third conductor is smaller than the bonding area between the heat sink and each semiconductor chip. In the state in which the back surface of the second conductor and the front surface of the third conductor are exposed, the semiconductor chips, the heat sink, the second conductor and the third conductor are sealed with a resin.
The semiconductor apparatus disclosed in Japanese Unexamined Patent Application Publication No. 2003-110064 includes a semiconductor device, a first metal body working as an electrode and as a radiator and bonded to the back surface of the semiconductor device, a second metal body working as an electrode and as a radiator and bonded on the front surface side of the semiconductor device, and a third metal body bonded between the semiconductor device surface and the second metal body. Almost the entire semiconductor apparatus is molded with a resin. The semiconductor device is made to be thin to reduce the shearing stress in the semiconductor device surface or to reduce the stress components in the bonding layers, through which the semiconductor device and the metal bodies are bonded, and the entire apparatus is restrained by the mold resin. The bonding layers are made from a solder containing tin as the main component thereof (hereinafter referred to as a “Sn solder”).
The semiconductor apparatus proposed in the following Japanese Patent Publication No. 3823974 includes a semiconductor device between a pair of metal plates. Almost the entire semiconductor apparatus is molded with a resin. The semiconductor apparatus proposed in Japanese Patent Publication No. 3823974 facilitates preventing the malfunction of the semiconductor device caused by the movement of the metal plate in the final stage of bonding thereof to the semiconductor chip from occurring and the life thereof from being shortened.
In bonding the surface electrodes of the semiconductor device with a solder in practice, it is necessary to plate Ni and such a metal onto the surface electrodes. For the plating, the electrolytic plating method or the electroless plating method may be employed generally. The electrolytic plating method feeds an external current to reduce the metal ions in a solution and to precipitate the metal atoms. The electroless plating method reduces the metal ions in a solution chemically without using electricity to precipitate metal atoms (cf. the Denki Mekki Kenkyuukai (The Society for the Study of Electrolytic Plating), “Mudenkai Mekki Kiso to Ohyo (Electroless Plating Fundamentals and Applications)” (in Japanese), published in May, 1994 by Business & Technology Daily News (Nikkan Kogyo Shimbun Ltd.), pp. 1 to 238). The metal deposition by the electroless plating method facilitates simplifying the manufacturing installation and the manufacturing process as compared with the electrolytic plating method that needs an electric circuit including counter electrodes and a DC power supply.
Japanese Patent Publication No. 4344560 proposes a semiconductor chip as described below. The semiconductor chip proposed in Japanese Patent Publication No. 4344560 includes a semiconductor device including front surface electrodes, to the surfaces of which electroless plating is applied. The semiconductor device includes also a back surface electrode bonded to the circuit pattern patterned on an insulator baseboard. The surface electrodes are bonded to connecting conductors. On an Al layer forming the surface electrode, a Ni layer and an Au layer laminated on the Ni layer are formed by electroless plating employing the zincate method such that the thermal conductivity of the electrode film is made to be uniform. The connecting conductor formed on the electrode film to constitute a heat dissipation path, and the electrode film, are bonded to each other via a lead-free solder layer.
FIG. 24 is a flow chart describing a conventional manufacturing method for manufacturing a semiconductor chip. First, the front surface structure of an IGBT including a base region and an emitter region is formed in the surface portion on the front surface side of a semiconductor wafer (step S101). An emitter electrode in contact with the base region and the emitter region is formed as a front surface electrode (step S102). A protector film made from polyimide is formed on the front surface of the semiconductor wafer and an opening is formed through the protector film such that the emitter electrode is exposed (step S103). The protector film covers the semiconductor wafer surface exposed to the front surface side. Back grinding and etching are conducted from the back surface side of the semiconductor wafer to thin the semiconductor wafer (step S104). Back surface semiconductor regions including a collector region are formed in the surface portion on the back surface side of the semiconductor wafer (step S105). A back surface electrode, in contact with the collector region and formed by laminating multiple metal electrode layers, is formed on the back surface of the semiconductor wafer (step S106). A supporting baseboard is stuck to the back surface of the semiconductor wafer (step S107). An electroless Ni—P/Au plate film formed of an electroless Ni-phosphorus (P) plate layer and an electroless Au plate layer is formed on the front surface of the semiconductor wafer by electroless plating (step S108). The semiconductor wafer is diced into semiconductor chips. The semiconductor chip, the surfaces of the front surface electrodes thereon are treated by electroless plating, is completed.
Japanese Unexamined Patent Application Publication No. 2005-353960 proposes a manufacturing method for manufacturing the semiconductor chip as described above. In applying an electroless plating treatment to the surface of the electrode terminal formed on the first surface side of a silicon wafer, the manufacturing method proposed in Japanese Unexamined Patent Application Publication No. 2005-353960 sticks a dicing tape to the entire second surface of the silicon wafer as an electrical insulating material. After insulating the entire second surface of the silicon wafer, the manufacturing method proposed in Japanese Unexamined Patent Application Publication No. 2005-353960 applies the electroless plating treatment to the surface of the electrode terminal.
Japanese Patent Publication No. 3829860 proposes a method for forming a front surface electrode on a semiconductor wafer in the state, in which the semiconductor wafer is fixed onto a supporting baseboard. A semiconductor chip is obtained by dicing the semiconductor wafer. The semiconductor chip includes electrodes on the major front and back surfaces thereof. Metal bodies, each functioning as an electrode and for a radiator, are arranged on the major front and back surface sides of the semiconductor chip. The semiconductor chip is mounted on a semiconductor apparatus, almost the entire of which is molded with a resin.
Japanese Patent Publication No. 4049035 proposes a method for forming a plate film on the front surface side of a semiconductor wafer to form a front surface electrode, for thinning the semiconductor wafer from the back surface side opposite to the front surface, and for forming a back surface electrode including a Ni film on the back surface of the thinned semiconductor wafer. The manufacturing method proposed in Japanese Patent Publication No. 4049035 thins the semiconductor wafer first and, then, forms the back surface electrode. After forming the back surface electrode, the manufacturing method proposed in Japanese Patent Publication No. 4049035 forms the plate film to form only the front surface electrode.
Japanese Unexamined Patent Application Publication No. 2009-054965 proposes a method as described below. A covering adhesive tape is stuck onto the back surface of a wafer, on which a back surface electrode film is formed. Then, the wafer, on which the covering adhesive tape is adhering, is dipped into an electroless Ni plating solution in a plating bath to form a Ni plate film on a wiring film formed on the wafer major surface. Then, an Au plate film is formed on the Ni plate film in the similar manner as the Ni plate film to form an under barrier metal plate film (UBM plate film) formed of the Ni and Au plate films. When the wafer major surface is bent such that the wafer major surface is shaped to be concave, the wafer, on which the covering adhesive tape is adhering, is treated thermally.
Japanese Patent Publication No. 4333650 discloses a method for applying a plating treatment to a semiconductor wafer supported by a dicing tape having a frame and for dicing the semiconductor wafer.
Japanese Patent Publication No. 3607143 proposes a method for sticking a protector tape to a semiconductor wafer. A semiconductor wafer, the position thereof is determined, is fed onto a mounting table, absorbed to the mounting table and fixed on the mounting table. A protector tape is cut by a protector tape cutter such that the size and the shape thereof coincide with the size and the shape of the semiconductor wafer. The non-adhesive surface of the cut protector tape is absorbed and held by an absorber table, moveable up and down, capable of shaking and moveable from the tape cutter to the mounting table. The absorber table in the tilting state thereof is moved above the mounting table such that the protector tape is right above the semiconductor wafer. The absorber table is made to descend such that the down side portion of the tilting protector tape is laid on the semiconductor wafer. The absorber table is made to shake in the vacuum atmosphere horizontally around the down side portion of the tilting absorber table for pressing to stick the entire adhesive surface of the protector tape onto the semiconductor wafer.
Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2006-520088 proposes a preliminary treatment method for treating an adhering surface in the case, in which another constituent element is stuck to a semiconductor chip. After one or more adhering surfaces are treated preliminary, adhesion is conducted to connect two or more baseboards to the semiconductor chip. A plasma is made to react to the one or more adhering surfaces under the atmospheric pressure as the preliminary treatment.
Japanese Unexamined Patent Application Publication No. 2006-156567 proposes a method as described below. A surface protector tape stuck to a semiconductor wafer includes a base material layer and an adhesive material layer. The base material layer has a slit on the surface thereof opposite to the surface in contact with the adhesive material layer. The base material layer may be treated physically or chemically to improve the adhesiveness thereof to the adhesive material layer coated afterward on the base material layer. The chemical treatment includes a plasma treatment.
Japanese Unexamined Patent Application Publication No. 2004-241443 proposes a method of cleaning the front and back surfaces of a semiconductor wafer in a plasma cleaning machine to remove organic deposits on a semiconductor wafer. The cleaned semiconductor wafer is stuck to a dicing sheet via a film adhesive to divide the semiconductor wafer into semiconductor devices together with the film adhesive thereon by dicing.
As the results of the researches explored vigorously by the present inventors, it has been found that the problems as described below will be caused, if a semiconductor chip is manufactured by any of the techniques disclosed by Japanese Patent Publication No. 3829860 and Japanese Unexamined Patent Application Publication No. 2009-054965.
FIGS. 19 through 22 are cross sectional views of a semiconductor wafer describing a conventional method of manufacturing a semiconductor chip. FIGS. 19 through 22 describe the steps subsequent to step S106 described in FIG. 24. In FIGS. 19 through 22, the front surface structure is not shown. In FIGS. 19 through 22, neither the emitter electrode nor the back surface electrode on the semiconductor wafer is shown.
As described in FIG. 19, semiconductor wafer 120 is bending convexly toward the front surface side due to the tensile stress caused by a back surface electrode after the formation thereof (cf. step S106 in FIG. 24). Semiconductor wafer 120 is bent convexly toward the front surface side, since the laminate film formed of metal layers and working as a back surface electrode generates a tensile stress greater than the tensile stress that the emitter electrode formed as a front surface electrode (cf. step S102 in FIG. 24) generates. If a thermal treatment is conducted, e.g., at 350° C., to reduce the contact resistance of the back surface electrode, a greater tensile stress will be caused on the back surface side of semiconductor wafer 120. When semiconductor wafer 120 is thinned to be from 80 to 140 μm in thickness (cf. step S104 in FIG. 24), the warp tW of semiconductor wafer 120 will be, for example, from 1 to 8 mm (cf. FIG. 6 in Japanese Patent Publication No. 4049035).
The techniques disclosed in Japanese Patent Publication No. 3829860 and Japanese Unexamined Patent Application Publication No. 2009-054965 rid semiconductor wafer 120 of the warp tW as described above. Supporting baseboard 121 stuck to the back surface of semiconductor wafer 120 as shown in FIG. 20 rids semiconductor wafer 120 of the warp tW (cf. step S107 in FIG. 24 and Japanese Patent Publication No. 3829860), since the stress large enough to keep semiconductor wafer 120 flat is exerted to semiconductor wafer 120 from supporting baseboard 121.
Even if plate film 122 is formed on the front surface of semiconductor wafer 120 as described in FIG. 21 (cf. step S108 in FIG. 24) and a tensile stress is caused by plate film 122 on the front surface side of semiconductor wafer 120, semiconductor wafer 120 will keep the flat state thereof, since semiconductor wafer 120 is supported by supporting baseboard 121.
Even if the semiconductor wafer happens to bend concavely toward the front surface side due to the plate film formed on the front surface of the semiconductor wafer, the warp caused in the semiconductor wafer will be gotten rid of by heating the tape stuck to the back surface of the semiconductor wafer to exert tension to the tape by the technique disclosed in Japanese Unexamined Patent Application Publication No. 2009-054965. This situation is not illustrated.
The techniques disclosed in Japanese Patent Publication No. 3829860 and Japanese Unexamined Patent Application Publication No. 2009-054965 rid the semiconductor wafer of the warp thereof. However, it has been revealed that the semiconductor wafer will bend again, when the supporting baseboard or the tape stuck to the back surface of the semiconductor wafer is removed. For example, if the supporting baseboard stuck to the back surface of semiconductor wafer 120 is removed as shown in FIG. 22, semiconductor wafer 120 will bend concavely toward the front surface side in opposite to the state before the supporting baseboard is stuck (cf. FIG. 19). The reason for this may be estimated as described below.
Semiconductor wafer 120 is forced to be in the flat state by the stress exerted from supporting baseboard 121. The flat state is maintained on the back surface side of semiconductor wafer 120, after supporting baseboard 121 is removed. On the front surface side of semiconductor wafer 120, a tensile stress is caused by plate film 122 formed on the front surface of semiconductor wafer 120. Therefore, semiconductor wafer 120 is bent concavely toward the front surface side from the flat state contrary to the descriptions of the techniques described in the Japanese Patent Publication No. 3829860. Therefore, it is estimated that the semiconductor wafer bends again as a further stress is exerted thereto in the state, in which the semiconductor wafer is maintained to be flat, or as the stress for maintaining the semiconductor wafer in the flat state thereof is removed.
FIG. 23 is a cross sectional view of a semiconductor chip, in which a warp is caused. In FIG. 23, the front surface structure is not shown. In FIG. 23, neither the emitter electrode nor the back surface electrode on the semiconductor wafer is shown.
Semiconductor chip 101 in FIG. 23 is manufactured by dicing (cutting) the semiconductor wafer bending concavely toward the front surface side (cf. FIG. 22) into chips. It has been found that semiconductor chip 101 will bend concavely toward the front surface side, when semiconductor chip 101 is obtained by dicing the semiconductor wafer bending concavely toward the front surface side. In other words, a warp tC is caused in semiconductor chip 101 in the same direction as the warp caused in the semiconductor wafer bending concavely toward the front surface side.
When semiconductor chip 101 is bending as long as 30 μm, the problems as described below will be caused. In measuring the electric characteristics of semiconductor chip 101 in the shipping inspections or in screening the defective chips, semiconductor chip 101 will not be absorbed to a carrier hand nor to a measuring stage or semiconductor chip will 101 not be absorbed at the right position on the measuring stage. Then, the electric characteristics of the semiconductor device formed in semiconductor chip 101 will not be measured accurately.
In bonding a metal plate to semiconductor chip 101 with a solder, the solder layer thickness between semiconductor chip 101 and the metal plate is designed to be from 70 to 130 μm. If semiconductor chip 101 is bending as long as 30 μm, voids will be caused in the solder layer by the warp tC of semiconductor chip 101, when semiconductor chip 101 is mounted by bonding with a solder. Due to the voids caused, semiconductor chip 101 will be displaced from the right position or it will be impossible to mount semiconductor chip 101. Therefore, the throughput of non-defective semiconductor apparatus products will be impaired. Due to the voids caused, the reliability of the semiconductor apparatus will be lowered.
Or else, the entire solder layer or a part of the solder layer is thinned due to the warp tC of semiconductor chip 101, resulting in the short life of the semiconductor apparatus or the lower reliability of the semiconductor apparatus. Further, semiconductor chip 101 or the metal plate may be displaced from the right bonding position or a short-circuit fault may be caused due to the warp tC of semiconductor chip 101, resulting in the low throughput of non-defective semiconductor apparatus products.
As for the technique disclosed in Japanese Unexamined Patent Application Publication No. 2009-054965, when the adhesiveness between the back surface electrode and the tape is low, the tape may peel off the semiconductor wafer and the plating solution may come in between the semiconductor wafer and the tape. If the back surface electrode is exposed to the plating solution, the plating material will segregate abnormally on the back surface electrode, the edge portion surface of the surface electrode will be tarnished (hereinafter referred to as “external appearance anomalies”), and such a new problem will be caused. If external appearance anomalies are caused on the back surface electrode, the wettability of the back surface electrode to the solder will be impaired. If the wettability of the back surface electrode to the solder is not good, voids will be caused in the boundary between the back surface electrode and the solder layer in mounting the semiconductor device by bonding with a solder. The voids caused will lower the reliability of the semiconductor apparatus.
In view of the foregoing, it is a first object of the invention to obviate the problems described above. It is a second object of the invention to provide a method of manufacturing a semiconductor apparatus that facilitates improving the reliability of the semiconductor apparatus. It is a third object of the invention to provide a method of manufacturing a semiconductor apparatus that facilitates improving the throughput of the non-defective semiconductor apparatus products. It is a fourth object of the invention to provide a method of manufacturing a semiconductor apparatus that facilitates preventing the external appearance anomalies of the surface electrodes from occurring.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.